{
switch (pib_off) {
case PIB_OFST_INTA:
- panic("Undefined write on PIB INTA\n");
+ panic_domain(NULL,"Undefined write on PIB INTA\n");
break;
case PIB_OFST_XTP:
if ( s == 1 && ma == 4 /* UC */) {
vmx_vcpu_get_plat(vcpu)->xtp = *(uint8_t *)src;
}
else {
- panic("Undefined write on PIB XTP\n");
+ panic_domain(NULL,"Undefined write on PIB XTP\n");
}
break;
default:
if ( PIB_LOW_HALF(pib_off) ) { // lower half
if ( s != 8 || ma != 0x4 /* UC */ ) {
- panic("Undefined IPI-LHF write with s %ld, ma %d!\n", s, ma);
+ panic_domain
+ (NULL,"Undefined IPI-LHF write with s %ld, ma %d!\n", s, ma);
}
else {
write_ipi(vcpu, pib_off, *(uint64_t *)src);
}
else { // upper half
printf("IPI-UHF write %lx\n",pib_off);
- panic("Not support yet for SM-VP\n");
+ panic_domain(NULL,"Not support yet for SM-VP\n");
}
break;
}
// TODO: INTA read from IOSAPIC
}
else {
- panic("Undefined read on PIB INTA\n");
+ panic_domain(NULL,"Undefined read on PIB INTA\n");
}
break;
case PIB_OFST_XTP:
*((uint8_t*)dest) = vmx_vcpu_get_plat(vcpu)->xtp;
}
else {
- panic("Undefined read on PIB XTP\n");
+ panic_domain(NULL,"Undefined read on PIB XTP\n");
}
break;
default:
if ( PIB_LOW_HALF(pib_off) ) { // lower half
if ( s != 8 || ma != 4 ) {
- panic("Undefined IPI-LHF read!\n");
+ panic_domain(NULL,"Undefined IPI-LHF read!\n");
}
else {
#ifdef IPI_DEBUG
}
else { // upper half
if ( s != 1 || ma != 4 ) {
- panic("Undefined PIB-UHF read!\n");
+ panic_domain(NULL,"Undefined PIB-UHF read!\n");
}
else {
#ifdef IPI_DEBUG
vio = get_vio(v->domain, v->vcpu_id);
if (vio == 0) {
- panic("bad shared page: %lx", (unsigned long)vio);
+ panic_domain(NULL,"bad shared page: %lx", (unsigned long)vio);
}
p = &vio->vp_ioreq;
p->addr = pa;
vio = get_vio(v->domain, v->vcpu_id);
if (vio == 0) {
- panic("bad shared page\n");
+ panic_domain(NULL,"bad shared page\n");
}
p = &vio->vp_ioreq;
p->addr = TO_LEGACY_IO(pa&0x3ffffffUL);
legacy_io_access(vcpu, src_pa, dest, s, dir);
break;
default:
- panic("Bad I/O access\n");
+ panic_domain(NULL,"Bad I/O access\n");
break;
}
return;
uint64_t pa;
if (!vtlb->nomap)
- panic("Normal memory write shouldn't go to this point!");
+ panic_domain(NULL,"Normal memory write shouldn't go to this point!");
pa = PPN_2_PA(vtlb->ppn);
pa += POFFSET((u64)src, vtlb->ps);
break;
case 2: // PMI
// TODO -- inject guest PMI
- panic ("Inject guest PMI!\n");
+ panic_domain (NULL, "Inject guest PMI!\n");
break;
case 4: // NMI
vmx_vcpu_pend_interrupt (vcpu, 2);
break;
case 5: // INIT
// TODO -- inject guest INIT
- panic ("Inject guest INIT!\n");
+ panic_domain (NULL, "Inject guest INIT!\n");
break;
case 7: // ExtINT
vmx_vcpu_pend_interrupt (vcpu, 0);
case 3:
case 6:
default:
- panic ("Deliver reserved IPI!\n");
+ panic_domain (NULL, "Deliver reserved IPI!\n");
break;
}
}
target_cpu = lid_2_vcpu(vcpu->domain,
((ipi_a_t)addr).id, ((ipi_a_t)addr).eid);
- if ( target_cpu == NULL ) panic("Unknown IPI cpu\n");
+ if ( target_cpu == NULL ) panic_domain (NULL,"Unknown IPI cpu\n");
if ( target_cpu == vcpu ) {
// IPI to self
deliver_ipi (vcpu, ((ipi_d_t)value).dm,
}
else {
// TODO: send Host IPI to inject guest SMP IPI interruption
- panic ("No SM-VP supported!\n");
+ panic_domain (NULL, "No SM-VP supported!\n");
return 0;
}
}
}
}
- // Floating-point Load/Store
+ // Floating-point spill + Imm update
+ else if(inst.M10.major==7&&inst.M10.x6==0x3B){
+ struct ia64_fpreg v;
+ inst_type=SL_FLOATING;
+ dir=IOREQ_WRITE;
+ vcpu_get_fpreg(vcpu,inst.M10.f2,&v);
+ vcpu_get_gr_nat(vcpu,inst.M10.r3,&temp);
+ post_update = (inst.M10.i<<7)+inst.M10.imm7;
+ if(inst.M10.s)
+ temp -= post_update;
+ else
+ temp += post_update;
+ vcpu_set_gr(vcpu,inst.M10.r3,temp,0);
+
+ /* Write high word.
+ FIXME: this is a kludge! */
+ v.u.bits[1] &= 0x3ffff;
+ mmio_access(vcpu, padr + 8, &v.u.bits[1], 8, ma, IOREQ_WRITE);
+ data = v.u.bits[0];
+ size = 3;
+ }
+ // Floating-point stf8 + Imm update
+ else if(inst.M10.major==7&&inst.M10.x6==0x31){
+ struct ia64_fpreg v;
+ inst_type=SL_FLOATING;
+ dir=IOREQ_WRITE;
+ size=3;
+ vcpu_get_fpreg(vcpu,inst.M10.f2,&v);
+ data = v.u.bits[0]; /* Significand. */
+ vcpu_get_gr_nat(vcpu,inst.M10.r3,&temp);
+ post_update = (inst.M10.i<<7)+inst.M10.imm7;
+ if(inst.M10.s)
+ temp -= post_update;
+ else
+ temp += post_update;
+ vcpu_set_gr(vcpu,inst.M10.r3,temp,0);
+ }
// else if(inst.M6.major==6&&inst.M6.m==0&&inst.M6.x==0&&inst.M6.x6==3){
// inst_type=SL_FLOATING; //fp
// dir=IOREQ_READ;
// size=3; //ldfd
// }
+ // lfetch - do not perform accesses.
+ else if(inst.M15.major==7&&inst.M15.x6>=0x2c&&inst.M15.x6<=0x2f){
+ vcpu_get_gr_nat(vcpu,inst.M15.r3,&temp);
+ post_update = (inst.M15.i<<7)+inst.M15.imm7;
+ if(inst.M15.s)
+ temp -= post_update;
+ else
+ temp += post_update;
+ vcpu_set_gr(vcpu,inst.M15.r3,temp,0);
+
+ vmx_vcpu_increment_iip(vcpu);
+ return;
+ }
else{
- printf("This memory access instruction can't be emulated two: %lx\n ",inst.inst);
- while(1);
+ panic_domain
+ (NULL,"This memory access instr can't be emulated: %lx pc=%lx\n ",
+ inst.inst, regs->cr_iip);
}
size = 1 << size;
if(inst_type==SL_INTEGER){ //gp
vcpu_set_gr(vcpu,inst.M1.r1,data,0);
}else{
- panic("Don't support ldfd now !");
+ panic_domain(NULL, "Don't support ldfd now !");
/* switch(inst.M6.f1){
case 6:
struct { unsigned long qp:6, f1:7, un7:7, r3:7, x:1, hint:2, x6:6, m:1, major:4; };
} INST64_M6;
+typedef union U_INST64_M9 {
+ IA64_INST inst;
+ struct { unsigned long qp:6, :7, f2:7, r3:7, x:1, hint:2, x6:6, m:1, major:4; };
+} INST64_M9;
+
+typedef union U_INST64_M10 {
+ IA64_INST inst;
+ struct { unsigned long qp:6, imm7:7, f2:7, r3:7, i:1, hint:2, x6:6, s:1, major:4; };
+} INST64_M10;
+
+typedef union U_INST64_M15 {
+ IA64_INST inst;
+ struct { unsigned long qp:6, :7, imm7:7, r3:7, i:1, hint:2, x6:6, s:1, major:4; };
+} INST64_M15;
+
typedef union U_INST64 {
IA64_INST inst;
struct { unsigned long :37, major:4; } generic;
INST64_M4 M4; // st integer
INST64_M5 M5;
INST64_M6 M6; // ldfd floating pointer
+ INST64_M9 M9; // stfd floating pointer
+ INST64_M10 M10; // stfd floating pointer
+ INST64_M15 M15; // lfetch + imm update
INST64_M28 M28; // purge translation cache entry
INST64_M29 M29; // mov register to ar (M unit)
INST64_M30 M30; // mov immediate to ar (M unit)
projects / xen.git / commitdiff